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www.fairchildsemi.com rev. 1.0.2 8/26/04 features output range 0.8v to v in 0.8v internal reference ?.5% over line voltage and temperature drives n-channel mosfets simple single-loop control design ? oltage-mode pwm control ? ast transient response high-bandwidth error ampli?r full 0% to 100% duty cycle lossless, programmable over-current protection uses upper mosfets r ds(on) small converter size 300khz fixed frequency oscillator internal soft-start 8-lead soic applications ? o wer supplies for pc subsystems and peripherals mch, gtl, and agp supplies cable modems, set top boxes, and dsl modems dsp, memory ? o w-voltage distributed power supplies general description the fan6520a makes simple work out of implementing a complete control and protection scheme for a dc-dc stepdown converter. designed to drive n-channel mosfets in a synchronous b uck topology, the fan6520a integrates the control, output adjustment, monitoring and protection functions into a single 8-lead package. the fan6520a is easy to use, employs a single feedback loop, and voltage-mode control with fast transient response. the output voltage can be precisely regulated to as low as 0.8v, with a maximum tolerance of ?.5% over temperature and line voltage variations. a ?ed frequency oscillator reduces design complexity, while balancing typical application cost. the error ampli?r features a 15mhz gain- bandwidth product and an 8v/? slew rate which enables high converter bandwidth for fast transient performance. the resulting pwm duty cycles range from 0% to 100%. the ic monitors the drop across the upper mosfet and inhibits pwm operation appropriately to protect against ove r -current conditions. this approach simpli?s the implementation and improves ef?iency by eliminating the need for a current sense resistor. the fan6520a is rated for operation from 0?to +70? with the fan6520ai rated from ?0?to +85?. f an6520a single synchronous buck pwm controller
2 rev. 1.0.2 8/26/04 fan6520a product specification pin con?uration fan6520am 8-pin soic package pin de?itions pin # pin name pin function description 1 boot bootstrap supply input. provides a boosted voltage to the high-side mosfet driver. connect to bootstrap capacitor as shown in figure 1. 2 hdrv high side gate drive output. connect to the gate of the high-side power mosfet(s). this pin is also monitored by the adaptive shoot-through protection circuitry to determine when the upper mosfet has turned off. 3 gnd ground. the signal and power ground for the ic. tie this pin to the ground island/plane through the lowest impedance connection available. connect directly to source of low-side mosfet(s). 4 ldrv low side gate drive output. connect to the gate of the low-side power mosfet(s). this pin is also monitored by the adaptive shoot-through protection circuitry to determine when the lower mosfet has turned off. 5 vcc vcc. provides bias power to the ic and the drive voltage for ldrv. bypass with a ceramic capacitor as close to this pin as possible. 6fb feedback. this pin is the inverting input of the internal error ampli?r. use this pin, in combination with the comp/ocset pin, to compensate the voltage-control feedback loop of the converter. 7 comp/ ocset/sd comp/ocset/sd. this is a multiplexed pin. during operation, the output of the error ampli?r drives this pin. during a short period of time following power-on reset (por), this pin is used to determine the over-current threshold of the converter. pulling comp/ocset to a level below 0.8v disables the controller. disabling the controller causes the oscillator to stop, the hdrv and ldrv outputs to be held low, and the soft-start circuitry to re-arm. 8sw switch node input. connect as shown in figure 1. the sw pin provides return for the high-side bootstrapped driver, is a sense point for the adaptive shoot-thru protection, and is used for monitoring the drop across q1s r ds(on) for current limit. fan6520a 1 2 3 4 8 7 6 5 sw comp/ocset/sd fb vcc boot hdrv gnd ldrv
3 rev. 1.0.2 8/26/04 fan6520a product specification t ypical application figure 1. typical application figure 2. functional block diagram fb fan6520a vcc +v out q2 comp/ocset r s gnd ldrv sw hdrv boot 5 3 4 8 2 1 6 7 q1 c hf r offset r ocset c f r f c i c boot d boot c bulk c vcc +5v l out c out inhibit pwm fb 0.8v error + amp comp/ocset 20a osc gate control logic oc gnd ldrv sw hdrv boot pwm por / soft start vcc sample & hold vcc + +
4 rev. 1.0.2 8/26/04 fan6520a product specification absolute maximum ratings absolute maximum ratings are the values beyond which the device may be damaged or have its useful life impaired. functional operation under these conditions is not implied. thermal information recommended operating conditions p arameter min. max. units vcc to gnd 6v vboot to gnd 15 v hdrv (v boot ?v sw ) 6v ldrv 0.5 6 v sw to pgnd continuous 0.5 6 v transient ( t < 50nsec, f < 500khz) 37 v all other pins 5.5 v p arameter min. typ. max. units storage temperature ?5 150 ? lead soldering temperature, 10 seconds 300 ? v apor phase, 60 seconds 215 ? infrared, 15 seconds 220 ? po w er dissipation (p d ), t a = 25? 715 mw thermal resistance ?junction to case jc 40 ?/w thermal resistance ?junction to ambient ja 140 ?/w p arameter conditions min. typ. max. units supply voltage vcc vcc to pgnd 4.5 5 5.5 v ambient temperature (t a )f an6520a 070c f an6520ai 40 85 ? j unction temperature (t j ) 40 125 ?
product specification fan6520a rev. 1.0.2 8/26/04 5 electrical speci?ations vcc = 5v, and ta = 25? using circuit in figure 1 unless otherwise noted. the ?denotes speci?ations which apply over the full operating temperature range. notes: 1. all limits at operating temperature extremes are guaranteed by design, characterization and statistical quality control. 2. ac specifications guaranteed by design/characterization (not production tested). p arameter symbol conditions min. typ. max. units supply current vcc current i vcc hdrv, ldrv open 1.5 2.4 3.8 ma po wer-on reset rising vcc por threshold por 4.00 4.22 4.45 v vcc por threshold hysteresis 170 mv oscillator f requency f osc f an6520a 250 300 340 khz f an6520ai 230 300 340 khz ramp amplitude ? v osc 1.5 vp-p reference reference voltage v ref t a = 0 to 70? 788 800 812 mv f an6520ai 780 800 820 mv error ampli?r dc gain 88 db gain ?bandwidth product gbwp 15 mhz slew rate s/r 8 v/? gate drivers hdrv pull-up resistance r hup 2.5 ? hdrv pull-down resistance r hdn 2.0 ? ldrv pull-up resistance r lup 2.5 ? ldrv pull-down resistance r ldn 1.0 ? protection/disable ocset current source i ocset f an6520a 17 20 22 a f an6520ai 14 20 24 a disable threshold v disable 800 mv
6 rev. 1.0.2 8/26/04 fan6520a product specification circuit description initialization the fan6520a automatically initializes upon receipt of power. the power-on reset (por) function continually monitors the bias voltage at the vcc pin. when the supply v oltage exceeds its por threshold, the ic initiates the over-current protection (ocp) sample and hold operation. upon completion of the ocp sampling and hold operation, the por function initiates the soft-start operation. over-current protection the over-current function protects the converter from a shorted output by using the upper mosfets on-resistance, r ds(on) , to monitor the current. this method enhances the converters ef?iency and reduces cost by eliminating the need for a current-sensing resistor. the over-current function c ycles the soft-start function in a hiccup mode to provide f ault protection. a resistor (r ocset ) programs the over- current trip level (see typical application diagram). immediately following por, the fan6520a initiates the over-current protection sampling and hold operation. first, the internal error ampli?r is disabled. this allows an inter- nal 20? current sink to develop a voltage across r ocset . the fan6520a then samples this voltage at the comp pin. this sampled voltage, which is referenced to the vcc pin, is held internally as the over-current set point. when the v oltage across the upper mosfet, which is also referenced to the vcc pin, exceeds the over-current set point, the ove r -current function initiates a soft-start sequence. figure 3 shows the inductor current after a fault is introduced while running at 15a. the continuous fault causes the fan6520a to go into a hiccup mode with a typical period of 25ms. the inductor current increases to 18a during the soft-start inter- v al and causes an over-current trip. the converter dissipates v ery little power with this method. the measured input power for the conditions shown in figure 3 is only 1.5w. figure 3. over-current operation the over-current function will trip at a peak inductor current (i peak ) determined by: where i ocset is the internal ocset current source (20? typical). the oc trip point varies mainly due to the mosfets r ds(on) variations. to avoid over-current tripping in the normal operating load range, ?d the r ocset resistor from the equation above with: 1. the maximum r ds(on) at the highest junction temperature. 2. the minimum i ocset from the speci?ation table. 3. determine i peak for , where ? i is the output inductor ripple current. f or an equation for the ripple current see ?utput inductor (l out )?under component selection. internal circuitry of the fan6520a will not recognize a volt- age drop across r ocset larger than 0.5v. any voltage drop across r ocset that is greater than 0.5v will set the overcur- rent trip point to: an overcurrent trip cycles the soft-start function. soft-start the por function initiates the soft-start sequence after the ove r -current set point has been sampled. soft-start clamps the error ampli?r output (comp pin) and reference input (noninverting terminal of the error amp) to the internally generated soft-start voltage. figure 4 shows a typical start up interval where the comp/ocset pin has been released from a grounded (system shutdown) state. initially, the comp/ocset is used to sample the over-current setpoint by disabling the error ampli?r and drawing 20? through r ocset . once the over-current level has been sampled, the soft-start function is initiated. the clamp on the error ampli?r (comp/ocset pin) initially controls the converters output voltage during soft-start. the oscillators triangular waveform is compared to the ramping error ampli?r voltage. this generates sw pulses of increasing width that charge the output capacitor(s). when the inter- nally generated soft-start voltage exceeds the feedback (fb pin) voltage, the output voltage is in regulation. this method provides a rapid and controlled output voltage rise. the entire startup sequence typically takes about 11ms. output inductor current 5a/div. i peak i ocset r ocset r ds on () ----------------------------------------------- = (1) i peak i out max () ? i 2 ----- + > i peak 0.5v r ds on () ---------------------- =
product specification fan6520a rev. 1.0.2 8/26/04 7 figure 4. soft-start interval the fan6520a incorporates a mosfet shoot-through protection method which allows a converter to both sink and source current. care should be exercised when designing a converter with the fan6520a when it is known that the converter may sink current. when the converter is sinking current, it is behaving as a boost converter that is regulating its input voltage. this means that the converter is boosting current into the vcc rail, which supplies the bias voltage to the fan6520a. if this current has nowhere to go?uch as to other distrib- uted loads on the vcc rail, through a voltage limiting pro- tection device, or other methods?he capacitance on the vcc bus will absorb the current. this situation will allow the voltage level of the vcc rail to increase. if the voltage level of the rail is boosted to a level that exceeds the maxi- mum voltage rating of the fan6520a, then the ic will expe- rience an irreversible failure and the converter will no longer be operational. ensure that there is a path for the current to follow other than the capacitance on the rail to prevent this f ailure mode. application guidelines layout considerations as in any high frequency switching converter, layout is very important. switching current from one power device to another can generate voltage transients across the imped- ances of the interconnecting bond wires and circuit traces. use wide, short-printed circuit traces to minimize these interconnecting impedances. the critical components should be located as close together as possible, using ground plane construction or single point grounding. figure 5. printed circuit board power and ground planes or islands figure 5 shows the critical power components of the con- v erter. to minimize the voltage overshoot, the interconnect- ing wires indicated by heavy lines should be part of a ground or power plane in a printed circuit board. the components shown in figure 5 should be located as close together as possible. please note that the capacitors c in and c out may each represent numerous physical capacitors. locate the f an6520a within two inches of the q1 and q2 mosfets. the circuit traces for the mosfets gate and source con- nections from the fan6520a must be sized to handle up to 1a peak current. figure 5 shows the circuit traces that require additional layout consideration. use single point and ground plane construction for the circuits shown. minimize any leakage current paths on the comp/ocset pin and locate the resistor, r oscet close to the comp/ocset pin because the internal current source is only 20?. provide local vcc decoupling between vcc and gnd pins. locate the capaci- tor, cboot as close as practical to the boot and phase pins. all components used for feedback compensation should be located as close to the ic as practical. figure 6. pc board small signal layout guidelines +v out q2 ldrv sw hdrv q1 c in l out c out load vin fan 6520a q2 vcc sw boot q1 l out c out load gnd c boot c vcc +5v d boot comp/ocset +5v r ocset vin
8 rev. 1.0.2 8/26/04 fan6520a product specification feedback compensation figure 7 highlights the voltage-mode control loop for a synchronous-recti?d buck converter. the output voltage (v out ) is regulated to the reference voltage level. the error ampli?r (error amp) output (v e/a ) is compared with the oscillator (osc) triangular wave to provide a pulse-width modulated (pwm) wave with an amplitude of v in at the sw node. the pwm wave is smoothed by the output lc ?ter (l out and c out ). figure 7. voltage mode buck converter compensation design the modulator transfer function is the small-signal transfer function of v out /v comp . this function is dominated by a dc gain and the output ?ter (l out and c out ), with a double pole break frequency at f lc and a zero at f esr . the dc gain of the modulator is simply the input voltage (v in ) divided by the peak-to-peak oscillator voltage ? v osc . the following equations de?e the modulator break frequencies as a function of the output lc ?ter: 1. the compensation network consists of the error ampli- ?r (internal to the fan6520a) and the impedance networks z in and z fb . the goal of the compensation network is to provide a closed loop transfer function with the highest 0db crossing frequency (f 0db ) and adequate phase margin. phase margin is the difference between the closed loop phase at f 0db and 180 degrees. the equations below relate the compensation networks poles, zeros and gain to the components (r1, r2, r3, c1, c2, and c3) in figure 7. use the following steps to locate the poles and zeros of the compensation network: 2. pick gain (r2/r1) for the desired converter bandwidth. 3. place 1 st zero below the ?ters double pole (~75% f lc ). 4. place 2 nd zero at ?ters double pole. 5. place 1 st pole at the esr zero. 6. place 2 nd pole at half the switching frequency. 7. check gain against the error ampli?rs open-loop gain. 8. estimate phase margin. repeat if necessary. figure 8 shows an asymptotic plot of the dc-dc converters g ain vs. frequency. the actual modulator gain has a high g ain peak due to the high q factor of the output ?ter and is not shown in figure 8. using the above guidelines should give a compensation gain similar to the curve plotted. the open loop error ampli?r gain bounds the compensation g ain. check the compensation gain at fp2 with the capabili- ties of the error ampli?r. the closed loop gain is con- structed on the graph of figure 8 by adding the modulator gain (in db) to the compensation gain (in db). this is equivalent to multiplying the modulator transfer function by the compensation transfer function and plotting the gain. the compensation gain uses external impedance networks z fb and z in to provide a stable, high bandwidth (bw) ov erall loop. a stable control loop has a gain crossing with a ?0db/decade slope and a phase margin greater than 45? include worst case component variations when determining phase margin. z fb comp fb +v out q2 l out c out +5v vin sw esr 0.8v error amp pwm osc detailed compensation components comp fb 0.8v error amp c1 r2 c3 r3 c2 r1 z in v out z fb z in f lc 1 2 lc ------------------------- = (15) f esr 1 2 esr c ------------------------------------ = (16) f z1 1 2 r 2 c 1 --------------------- - = (17) f p1 1 2 r 2 c 1 c 2 c 1 c 2 + -------------------- ?? ?? ---------------------------------------- - = (18) f z2 1 2 c 3 r 1 r 3 + () --------------------------------------- - = (19) f p2 1 2 r 3 c 3 --------------------- - = (20)
product specification fan6520a rev. 1.0.2 8/26/04 9 figure 8. asymptotic bode plot of converter gain an output capacitor is required to ?ter the output and supply the load transient current. the ?tering requirements are a function of the switching frequency and the ripple current. the load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. these requirements are generally met with a mix of capaci- tors and careful layout. component selection output capacitors (c out ) modern components and loads are capable of producing transient load rates above 1a/ns. high frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. effective series resistance (esr) and voltage rating are typically the prime consider- ations for the bulk ?ter capacitors, rather than actual capaci- tance requirements. high-frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. be careful not to add inductance in the circuit board wiring that could cancel the performance of these low inductance components. consult with the load manufacturer on speci? decoupling requirements. use only specialized low-esr capacitors intended for switching- regulator applications for the bulk capacitors. the bulk capacitors esr will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. an aluminum electrolytic capacitors esr value is related to the case size with lower esr available in larger case sizes. how- ev er, the equivalent series inductance (esl) of these capac- itors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. unfortu- nately, esl is not a speci?d parameter. work with your capacitor supplier and measure the capacitors impedance with frequency to select a suitable component. in most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. output inductor (l out ) the output inductor is selected to meet the output voltage ripple requirements and minimize the converters response time to the load transient. the inductor value determines the converters ripple current and the ripple voltage is a function of the ripple current. the ripple voltage ( ? v) and current ( ? i) are approximated by the following equations: increasing the inductance value reduces the ripple current and voltage. however, a large inductance value reduces the converters ability to quickly respond to a load transient. one of the parameters limiting the converters response to a load transient is the time required to change the inductor current. given a suf?iently fast control loop design, the fan6520a will provide either 0% or 100% duty cycle in response to a load transient. the response time is the time required to slew the inductor current from an initial current value to the transient current level. during this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor. minimizing the response time can minimize the output capacitance required. depending upon the whether there is a load application or a load removal, the response time to a load transient (i step ) is different. the following equations give the approximate response time interval for application and removal of a transient load: where t rise is the response time to the application of a positive i step , and t f all is the response time to a load removal (negative i step ). the worst case response time can be either at the application or removal of load. be sure to check both of these equations at the minimum and maximum output levels for the worst case response time. input capacitor selection use a mix of input bypass capacitors to control the voltage ov ershoot across the mosfets. use small ceramic capaci- tors for high-frequency decoupling and bulk capacitors to supply the current needed each time q1 turns on. place the small ceramic capacitors physically close to the mosfets and between the drain of q1 and the source of q2. the important parameters for the bulk input capacitor are the v oltage rating and the rms current rating. for reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and the largest 100 80 60 40 20 0 -20 -40 -60 10 100 1k 10k 100k frequency (hz) open loop error amp gain compensation gain closed loop gain modulator gain 20log (v in /dv osc ) 20log (r 2 /r 1 ) f z1 f z2 f p1 f lc f esr f p2 gain (db) 1m 10m ? i v in v out f sw l ----------------------------- - = ? v esr ? i (1) t rise li step v in v out ----------------------------- - = t fall li step v out ------------------------ =
10 rev. 1.0.2 8/26/04 fan6520a product specification rms current required by the circuit. the capacitor voltage rating should be at least 1.25 times greater than the maxi- mum input voltage and a voltage rating of 1.5 times is a conservative guideline. the rms current rating requirement (i rms ) for the input capacitor of a buck regulator is: where the converter duty cycle; . for a through-hole design, several electrolytic capacitors may be needed. for surface-mount designs, solid tantalum capaci- tors can be used, but caution must be exercised with regard to the capacitors surge current rating. the capacitors must be capable of handling the surge current at power-up. some capacitor series available from reputable manufacturers are surge current tested. bootstrap circuit the bootstrap circuit uses a charge storage capacitor (c boot ) and the internal diode, as shown in figure 1. selection of these components should be done after the high-side mosfet has been chosen. the required capacitance is determined using the following equation: where q g is the total gate charge of the high-side mosfet, and ? v boot is the voltage droop allowed on the high-side mosfet drive. to prevent loss of gate drive, the bootstrap capacitance should be at least 50 times greater than the c iss of q1. thermal considerations t otal device dissipation: p d = p q + p hdrv + p ldrv (4) where p q represents quiescent power dissipation: p q = v cc [4ma + 0.036 (f sw ?100)] (5) where f sw is switching frequency (in khz). p hdrv represents internal power dissipation of the upper fet driver. p hdrv = p h(r) p h(f) (6) where p h(r) and p h(f) are internal dissipations for the rising and falling edges respectively: where: p q1 = q g1 v gs(q1) f sw (9) where q g1 is total gate charge of q1 for its applied v gs . as described in the equations above, the total power con- sumed in driving the gate is divided in proportion to the resistances in series with the mosfet's internal gate node as shown in figure 9. figure 9. driver dissipation model r g is the polysilicon gate resistance, internal to the fet. r e is the external gate drive resistor implemented in many designs. note that the introduction of r e can reduce driver power dissipation, but excess r e may cause errors in the ?daptive gate drive?circuitry. for more information please refer to fairchild app note an-6003, ?hoot-through? in synchronous buck converters. (http://www.fairchildsemi.com/an/an/an-6003.pdf) p ldrv is dissipation of the lower fet driver. p ldrv = p l(r) p l(f) (10) where p h(r) and p h(f) are internal dissipations for the rising and falling edges, respectively: where: p q2 = q g2 v gs(q2) f sw (13) i rms i l dd 2 () = (2) d v out v in -------------- = c boot q g ? v boot ---------------------- = (3) p hr () p q1 r hup r hup r e r g ++ ------------------------------------------- = (7) p hf () p q1 r hdn r hdn r e r g ++ ------------------------------------------- - = (8) hdrv q1 g r g r e r hup boot sw r hdn s p lr () p q2 r lup r lup r e r g ++ ------------------------------------------ - = (11) p lf () p q2 r ldn r hdn r e r g ++ ------------------------------------------- - = (12)
product specification fan6520a rev. 1.0.2 8/26/04 11 po wer mosfet selection f or more information on mosfet selection for synchro- nous buck regulators, refer to: an-6005: synchronous buck mosfet loss calculations. this fairchild app note is located at: http://www.fairchildsemi.com/an/an/an-6005.pdf losses in a mosfet are the sum of its switching (p sw ) and conduction (p cond ) losses. in typical applications, the fan6520a converter's output v oltage is low with respect to its input voltage, therefore the lower mosfet (q2) is conducting the full load current for most of the cycle. therefore choose a mosfet for q2 which has low r ds(on) to minimize conduction losses. in contrast, the high-side mosfet (q1) has a much shorter duty cycle, and its conduction loss will therefore have less of an impact. q1, however, sees most of the switching losses, so q1s primary selection criteria should be gate charge. high-side losses figure 10 shows a mosfets switching interval, with the upper graph being the voltage and current on the drain to source and the lower graph detailing v gs vs. time with a constant current charging the gate. the x-axis, therefore, is also representative of gate charge (q g ) . c iss = c gd + c gs , and it controls t1, t2, and t4 timing. c gd receives the current from the gate driver during t3 (as v ds is falling). the gate charge (q g ) parameters on the lower graph are either speci?d or can be derived from the mosfets datasheet. assuming switching losses are about the same for both the rising edge and falling edge, q1s switching losses, occur during the shaded time when the mosfet has voltage across it and current through it. these losses are given by: p upper = p sw + p cond where: p upper is the upper mosfets total losses, and p sw and p cond are the switching and conduction losses for a given mosfet. r ds(on) is at the maximum junction temperature (t j ). t s is the switching period (rise or fall time) and is t2+t3 (figure 10). the drivers impedance and c iss determine t2 while t3s period is controlled by the drivers impedance and q gd . since most of t s occurs when v gs = v sp we can use a constant current assumption for the driver to simplify the calculation of t s : figure 10. switching losses and q g figure 11. drive equivalent circuit most mosfet vendors specify q gd and q gs . q g(sw) can be determined as: q g(sw) = q gd + q gs ?q th where q th is the gate charge required to get the mosfet to its threshold (v th ). for the high-side mosfet, v ds = v in , which can be as high as 20v in a typical portable application. care should also be taken to include the delivery of the mosfets gate power (p gate ) in calculating the power dissipation required for the fan6520a: p gate = q g vcc f sw (17) where q g is the total gate charge to reach vcc. p sw v ds i l 2 --------------------- 2 t s ?? ?? f sw = (14) p cond v out v in -------------- ?? ?? i out 2 r ds on () = (15 ) v sp t1 t2 t3 4.5v t4 t5 q g(sw) v ds i d q gs q gd v th v gs c iss c gd c iss c gd r d r gate c gs hdrv 5v sw vin g t s q gsw () i driver -------------------- - q gsw () vcc v sp r driver r gate + ------------------------------------------------ ?? ?? ----------------------------------------------------- - ? (16)
12 rev. 1.0.2 8/26/04 fan6520a product specification low-side losses q2, however, switches on or off with its parallel shottky diode conducting, therefore v ds 0.5v. since p sw is proportional to v ds , q2s switching losses are negligible and we can select q2 based on r ds(on) only. conduction losses for q2 are given by: p cond = (1-d) i out 2 r ds(on) (18) where r ds(on) is the r ds(on) of the mosfet at the highest operating junction temperature and is the minimum duty cycle for the converter. since d min < 20% for portable computers, (1-d) 1 produces a conservative result, further simplifying the calculation. the maximum power dissipation (p d(max ) ) is a function of the maximum allowable die temperature of the low-side mosfet, the j-a , and the maximum allowable ambient temperature rise: j-a , depends primarily on the amount of pcb area that can be devoted to heat sinking (see fairchild app note an-1029 for so-8 mosfet thermal information). d v out v in -------------- = p d max () t j max () t a max () ja ------------------------------------------------ - = (19)
product specification fan6520a rev. 1.0.2 8/26/04 13 t ypical application circuit figure 12. 5v to 1.5v 15a dc-dc converter evaluation board bill of materials (1.5v, 15 amps): ref des description manufacturer p/n qty c1 100pf capacitor, 603 any 1 c2 0.01? capacitor, 603 any 1 c3 not populated 0 c4 0.1? capacitor, 603 any 1 c5a,c5b 1? capacitor, 805 any 3 c6,c11 0.1? capacitor, 603 any 2 c7 not populated capacitor, 603 any 0 c9-10,c12,c13 1500? capacitor, 6.3v united chemi-con kzj6.3vb152m10x12ll 4 d1 diode, 30ma, 30v fairchild mmsd4148 1 l1 1.2? inductor intertechnical sc5015-1r2m 1 q1,q2 mosfet fairchild fdd6606 2 r1 2.2k ? 1% resistor, 603 any 1 r2 30.1k ? 1% resistor, 603 any 1 r3 not populated 0 r4 2.49k ? resistor, 603 any 1 r5 11.8k ? resistor, 603 any 1 r6 not populated resistor, 603 any 0 r7 0 ? resistor, 603 any 1 pb1 pushbutton, miniature digikey p8007s-nd 1 u1 single synchronous buck pwm fairchild fan6520a 1 tp1,2,3,4 test points keystone 1514-2 4 fb u1 fan6520a vcc +v out q2 comp/ocset r7 gnd ldrv sw hdrv boot 5 3 4 8 2 1 6 7 q1 c5a r4 r5 c2 r2 c1 c6 d1 c13 c4 +5v l out c9-10 sw1 c12 c5b c7 c3 r1 r3 c11 r6
14 rev. 1.0.2 8/26/04 fan6520a product specification dimensional outline drawing 0.15+0.10 -0.05 8 0 (r0.10) 0.70 0.20 (1.04) 1.75 max 1.45+0.05 -0.20 (r0.10) 0.50 1.27 see detail a notes: unless otherwise specified a) this package conforms to jedec ms-012, variation aa, issue c, dated may 1990. b) all dimensions are in millimeters. c) dimensions do not include mold flash or burrs. d) standard lead finish: 200 microinches / 5.08 microns min. lead/tin (solder) on copper. land pattern recommendation 0.36 seating plane 0.10 c c gage plane 3.81 0.25 0.19 1.00 6.75 4.75 detail a (0.33) 1.27 6.00 pin one indicator 4 8 1 c m b a 0.25 3.90 0.10 0.51 0.35 b 5 4.90 0.10 3.81 a scale: 2:1 0.50 0.25 x 45
8/26/04 0.0m 001 stock#ds505602 ? 2004 fairchild semiconductor corporation life support policy fairchild? products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. product specification fan6520a ordering information pa rt number temperature range package packing fan6520am 0? to 70? soic-8 rails fan6520amx 0? to 70? soic-8 tape and reel fan6520aim ?0? to 85? soic-8 rails FAN6520AIMX ?0? to 85? soic-8 tape and reel

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